Performance and Physical Attack Security of Lattice-Based Cryptography

Decanato - Facoltà di scienze informatiche

Data: 17 Dicembre 2020 / 12:30 - 14:30


You are cordially invited to attend the PhD Dissertation Defense of Andrés Felipe Valencia Patiño on Thursday December 17th, 2020 at 12:30 on MS Teams.

Quantum technology has significantly evolved in the last decades. This progress rises the expectations to have soon a quantum computer useful for practical applications. A quantum computer will accelerate machine learning, financial modelling, and molecular modelling, among other fields. Quantum computer will also facilitate solving the integer factorization problem and the discrete logarithm problem. Thus, quantum computing will make obsolete security algorithms based on the hardness of those two problems. Post-Quantum Cryptography (PQC) is a new area of research studying algorithms for classical computers that are resistant against attacks carried out with quantum computers. Lattice-Based Cryptography (LBC) is a family of PQC that offers outstanding performance and versatility compared with other PQC approaches. LBC algorithms must be mathematically secured and their implementations must be robust against physical attacks while maintaining a performance suitable for practical implementations. This thesis addresses two problems that limit the widespread of LBC: the physical security of real world implementations and the not always satisfactory performance (in terms of execution time and energy). Addressing physical security, the vulnerabilities against fault attacks of RLWE (Ring Learning With Errors) encryption, which is the foundation of complex lattice-based algorithms, are evaluated. Moreover, we explore the vulnerabilities of arithmetic units used in LBC against fault sensitivity attacks, with a dedicate framework. Then the framework was generalized to address other fault attacks. Related to performance we evaluate how to speed up LBC algorithms following two approaches: flexible hardware accelerators and instruction set extension. We got an average speed up along the investigated algorithms of 3.1x and an average energy-delay-product reduction of 2.8x using flexible accelerators. With the instruction set extension we got an speed up to 1.7x with a maximum area overhead of 13.8%.

Dissertation Committee:
- Prof. Cesare Alippi, Università della Svizzera italiana, Switzerland (Research Advisor)
- Dr. Francesco Regazzoni, Università della Svizzera italiana, Switzerland (Research co-Advisor)
- Prof. Laura Pozzi, Università della Svizzera italiana, Switzerland (Internal Member)
- Prof. Stefan Wolf, Università della Svizzera italiana, Switzerland (Internal Member)
- Dr-Ing. Thomas Poeppelmann, Infineon Technologies AG, Germany (External Member)
- Prof. Ilia Polian, University of Stuttgart, Germany (External Member)
- Prof. Patrick Schaumont, Virginia Tech, USA (External Member)