Less is more: efficient hardware design through Approximate Logic Synthesis

You are cordially invited to attend the PhD Dissertation Defense of Ilaria Scarabottolo on Thursday October 15th, 2020 at 10:00
Please note that given the updated Covid-19 restrictions, the Dissertation Defence will be held online.
You can join here

Abstract:
As energy efficiency becomes a crucial concern in almost every kind of digital application, Approximate Computing gains popularity as a potential answer to this ever-growing energy quest. Approximate Computing is a design paradigm particularly suited for error-resilient applications, where small losses in accuracy do not represent a significant reduction in the quality of the result. In these scenarios, energy consumption and resources employment (such as electric power, or circuit area) can be significantly improved at the expense of a slight reduction in output accuracy. While Approximate Computing can be applied at different levels, my research focuses on the design of approximate hardware. In particular, my work explores Approximate Logic Synthesis, where the hardware functionality is automatically tuned to obtain more efficient counterparts, while always controlling the entailed error. Functional modifications include, among others, removal or substitution of gates and signals. A fundamental prerequisite for the application of these modifications is an accurate error model of the circuit under exam. My Ph.D. research work has deeply concentrated on the derivation of accurate error models of a circuit. These can, in turn, guide Approximate Logic Synthesis algorithms to optimal solutions and avoid expensive, time-consuming simulations. A precise error model allows to fully explore the design space and, potentially, adjust the desired level of accuracy even at runtime. I have also contributed to the state-of-the-art in ALS techniques by devising a circuit pruning algorithm that produces efficient approximate circuits for given error constraints. The innovative aspect of my work is that it exploits circuit topology and graph partitioning to identify circuit portions that impact to a smaller extent on the final output. With this information, ALS algorithms can improve their efficiency by acting first on those less-influent portions. Indeed, this error characterisation proves to be very effective in guiding and modeling approximate synthesis.

Dissertation Committee:

• Prof. Laura Pozzi, Università della Svizzera italiana, Switzerland (Research Advisor)
• Prof. Cesare Alippi, Università della Svizzera italiana, Switzerland (Internal Member)
• Prof. Antonio Carzaniga, Università della Svizzera italiana, Switzerland (Internal Member)
• Prof. George Constantinides , Imperial College, London, UK (External Member)
• Prof. Joerg Henkel, Karlsruhe Institute of Technology (KIT), Germany (External Member)
• Prof. Akash Kumar, TU Dresden, Germany (External Member)