Parallel Ultra Low Power - PULP 2023


Staff - Faculty of Informatics

5 May 2023

We are currently in the middle of an open source hardware revolution. What started as a hobbyist approach and academic curiosity, is on its best way to become an established way of developing integrated circuits and computing systems both in academia and industry. One of the leading efforts in open source hardware comes from the Parallel Ultra Low Power (PULP) platform (, based on the open RISC-V instruction set architecture, led by Prof. Luca Benini from ETH Zürich and University of Bologna ( that started exactly 10 years ago. In this short time, this project has provided key components used in both industry and academia, more than 50 Systems-on-chip were manufactured at ETH Zürich alone and large industry consortia (e.g. were formed to support RISC-V cores developed by the PULP team. 

Conveniently situated between Zurich and Bologna, Lugano is the perfect host to celebrate the accomplishments of the first 10 years of PULP platform with a two day event organized by USI by Francesco Regazzoni from University of Amsterdam and USI and hosting the entire PULP team from ETH Zürich and University of Bologna and a number of international guests, past and present collaborators from industry and academia. The event will feature around twenty presentations organized in six technical sessions on Monday and Tuesday, held at the Auditorium of USI West Campus, as well as a short visit to Monte Bre and a dinner at the magnificent Villa Ciani with generous support from the City of Lugano.

USI is proud to host this event and will continue to play an important part in supporting open hardware, RISC-V and PULP in the next 10 years as well. 
The event will take place on 5th and 6th of June in the Auditorium of USI West campus, programme below:

Monday, June 5th, 2023
What have we accomplished
9:00 PULP: looking back and looking forward – Luca Benini
9:30 A look at key publications from PULP – Davide Rossi
10:00 Fifty ICs in ten years, a visual history - Frank K. Gürkaynak

Microcontroller verticals
11:00 Next stop XR: towards on-sensor PULP computing for micropower eXtended Reality Francesco Conti
11:30 Progress on Autonomous PULP-based Nano-drones – Daniele Palossi
12:00 Connecting to humans, biosignal processing and PULP - Simone Benatti, Sergei Vostrikov

PULP instances for High Performance
14:00 From Cores to Chiplets: PULP's Adventure in Open-Source HPC – Gianna Paulin
14:30 Diving into MemPool: Scaling the Shared-Memory Cluster to 256 Cores – Samuel Riedel
15:00 Carfield: The Open-Research Platform for Safety, Resilient and Time-Predictable Systems – Angelo Garofalo

Tuesday, June 6th, 2023
9:00 Accelerating Sparse and Irregular Workloads with Stream Extensions - Paul Scheffler, Chi Zhang
9:30 Neuromorphic Computing on PULP: Accelerating Spiking Neural Networks with Digital Hardware – Alfio di Mauro
10:00 Accelerating Transformers and Exploring Hyper-Dimensional Computing Near Memory - Gamze Islamoglu, Manuel Eggimann

Pulp SW environment
11:00 Compilers and OSes for the Future: Dreaming High-level Abstractions for the Low-level PULP Software Stack - Guiseppe Tagliavini, Robert Balas
11:30 Tools for automatic NN deployment for edge devices - Alessio Burello, Moritz Scherer
12:00 Virtual Platforms for PULP systems - Germain Haugou, Nazareno Bruschi

What is next for PULP, the next 10 years
14:00 Boosting PULP with Vector and Transprecision Computing - Matteo Perotti, Luca Bertaccini
14:30 One small step for men, one giant leap for PULP: Pulp for space applications - Yvan Tortorella, Michael Roigenmoser
15:00 TeraPool: Boosting Wireless Communications by Pooling 1000s Cores with PULP - Marco Bertuletti, Yichao Zhang
15:30 The key to scalability: High-performance and energy-efficient data movement - Thomas Benz, Tim Fischer