Reconfigurable Computing for All: And-Inverter Cones & Domain-Specific Hardware Synthesis Tools
Staff - Faculty of Informatics
Start date: 12 February 2015
End date: 13 February 2015
The Faculty of Informatics is pleased to announce a seminar given by David Novo
DATE: Thursday, February 12th 2015
PLACE: USI Lugano Campus, room SI-008, Informatics building (Via G. Buffi 13)
TIME: 09.30
ABSTRACT:
Field-Programmable Gate Arrays (FPGAs) are the most promising realization of reconfigurable computing. FPGAs can be programmed to implement any circuit by simply changing some configuration bits. FPGAs therefore provide a much faster design cycle than application-specific circuits, which require additional tedious steps such as physical design, fabrication and testing. Furthermore, FPGAs enable better OEM customer support since the reconfigurability can be used to fix bugs and even to perform design upgrades with a simple firmware update.
Although FPGAs enjoy all these advantages, they also suffer from two main drawbacks that have hindered their widespread use during their 20+ years history. In this talk, I will present my work towards tackling these two drawbacks, namely (1) the efficiency (i.e., area, delay and energy consumption) gap with respect to dedicated circuit implementations, and (2) the inaccessible programming model, which is inherited from circuit design and far from software-like productivity.
In the first part of the talk, I will introduce a totally new kind of reconfigurable device that took inspiration from some modern synthesizers, which represent circuits as networks of AND-invert operations. Accordingly, we propose a new FPGA logic element in the form of a binary tree of AND gates with conditional inversion to replace the (so far) unchallenged look-up tables. This new logic element is called an And-Inverter Cone and exhibits very interesting properties, such as the fact that the area grows only linearly in the number of inputs, which promises to shrink the aforementioned efficiency gap.
In the last part of talk, I will present a cost-effective approach to develop domain-specific High-Level Synthesis (HLS) tools. In particular, we leverage domain-specific languages (e.g., a language optimized to specify linear algebra) to express the application at a high level of abstraction while enabling the automatic generation of an efficient FPGA configuration that implements the specified functionality. Such an approach has the potential to expand the use of FPGAs to application/software programmers who will now be able concentrate only on functionality without bothering with the particular architectural details needed to enable a good use of the reconfigurable substrate.
BIO:
David Novo is a Post-doctoral researcher at the EPFL School of Computer and Communication Sciences, where he joined the Processor Architecture Laboratory (LAP) in November 2010. Previously, he conducted his doctoral research at the Wireless Group in the Interuniversity Microelectronics Centre (IMEC), receiving the Ph.D in Engineering from the Katholieke Universiteit Leuven (KUL) in 2010.
HOST: Prof. Laura Pozzi
