Compilation and Design Automation For Extensible Embedded Processors

Staff - Faculty of Informatics

Start date:

End date:

Mr. Paolo BONZINI, Wednesday May 27th, 2009 at 16:00, room SI-006

The dissertation committee is composed of:

  • Prof. Laura Pozzi, Università della Svizzera italiana, Switzerland (advisor)
  • Prof. Jason Cong, University of California, Los Angeles, USA (external member)
  • Prof. Tulika Mitra, National University of Singapore, Singapore (external member)
  • Prof. Wayne Wolf, Georgia Institute of Technology, USA (external member)
  • Prof. Walter Binder, Università della Svizzera italiana, Switzerland (internal member)
  • Prof. Matthias Hauswirth, Università della Svizzera italiana, Switzerland (internal member)

During the last few years, the attention to system-on-chip processors focused on customizability and specializing functional units for particular applications. Such processor extensions can increase performance in domains such as cryptography and DSP, without incurring the power cost of superscalar RISC processors and the complexity of entirely customized integrated circuits.

Since it is extremely desirable that tools automate the design of accelerator units as much as possible, compilation takes on a new extended meaning in this context—the compiler’s job is not only to produce optimized assembly code for a machine, but also to find the optimal machine for which to compile.

The two different subproblems involved in this task are to automatically generate the best instruction-set extensions (ISEs), and to use them extensions, i.e. finding them in the user’s applications. Therefore, most of the thesis deals with formalizing these combinatorial problems in general, characterizing them for particular architectures, reducing them whenever possible to well known graph optimization tasks, and solving them.

Another wholly different part of compilation for extensible embedded processors is to understand and solve the unique challenges that are posed to a compiler that can actually shape its target machine. In particular, existing compilation techniques can be redesigned and retuned to find even better instruction-set extensions—just like a general purpose compiler will transform the program to maximally exploit the target processor’s machine language. Since this subject exposes many different facets, this thesis touches areas such as compilation, combinatorial optimization, and hardware design. Results presented include: complexity proofs for several algorithms and problems from existing literature; a framework for automated discovery of custom instructions, which is reused in different contexts and for different customization technologies; and techniques for analyzing the effect of compiler optimizations on ISE search. All contributions are prototyped in complete compilation and simulation environments.