System-Level Memory Optimization for Heterogeneous System-on-Chip Architectures

The Faculty of Informatics is pleased to announce a seminar given by Christian Pilato

DATE: Friday, January 16th 2015
PLACE: USI Lugano Campus, room SI-004, Informatics building (Via G. Buffi 13)
TIME: 10.30

ABSTRACT:
The design of specialized accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an accelerator. To address these limitations, we present a novel methodology to automatically derive the memory subsystems of SoC accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the accelerator specifications.

BIO:
Christian Pilato received his Ph.D. in Information Technology from Politecnico di Milano in 2011 on his work on the integration and optimization of hardware accelerators in embedded systems at different levels of abstraction. From 2011 to 2013, he was a research associate with Politecnico di Milano and worked in the context of multiple EU-funded projects on the design and prototyping of FPGA reconfigurable systems, and on the optimization of design-for-manufacturing for design flows based on standard-cells. Since Sept. 2013, he has been a post-doc research scientist in the System-Level Design group at Columbia University, where is currently working on the design of high-performance and energy-efficient hardware accelerators through high-level synthesis, focusing on memory-related aspects, and system-level integration methods. He is also actively involved as program committee member in many conferences on embedded systems, CAD, and reconfigurable architectures.

HOSTS: Dr. Francesco Regazzoni, Prof. Miroslaw Malek