A Design Flow and Evaluation Framework for DPA-resistant Embedded Systems - A step towards design automation for security

On Tuesday December 15th, 2009 at 10h30 in the Red Building (room A23), Mr. Francesco REGAZZONI will defend his Ph.D. dissertation titled:

“A Design Flow and Evaluation Framework for DPA-resistant Embedded Systems - A step towards design automation for security”

The dissertation committee is composed of:

• Prof. Mariagiovanna Sami, Università della Svizzera Italiana, Lugano, Switzerland (research advisor)
• Prof. Laura Pozzi, Università della Svizzera Italiana, Lugano, Switzerland (co-advisor)
• Prof. Matthias Hauswirth, Università della Svizzera Italiana, Lugano, Switzerland (internal member)
• Prof. Thomas Shrimpton, Portland State University, Portland, Oregon, USA (external member)
• Prof. Pascal Junod, Haute Ecole d'Ingénierie et de Gestion, Yverdon-les-Bains, Switzerland (external member)
• Prof. William Fornaciari, Politecnico di Milano, Milano, Italy (external member)

ABSTRACT:

Security is a fundamental feature for nowadays embedded systems, but this need can not be satisfied anymore just by providing devices with a strong cryptographic algorithm. New, faster and cheaper attacks developed in the last years pose a serious threat for system designers.
Unlike mathematical approaches, the so called side channel attacks use the information leaked while data is being processed in order to derive the secret key. Side channel attacks based on power consumption are particularly dangerous, since they do not require a deep knowledge of the target device to be effective. In order to counteract such attacks, protected logic styles have been proposed as an alternative to CMOS and their results are promising. However, their area and power consumption are both significantly larger than for CMOS.

In embedded systems, the power budget is severely constrained, so that undue increase would not be acceptable. In view of this increasingly relevant problem, the final goal of this dissertation is to enable the efficient design of security-specific systems characterized by robustness with respect to attacks based on power-related side effects as well as by low-energy consumption and high performances.

In particular, we have developed a design flow which can automatically synthesize and place-and-route designs where CMOS and protected logic styles can be combined. The flow is integrated into a simulation and evaluation environment to quantify on a sound basis the achieved resistance against power analysis attacks. Our results proved the feasibility of an hybrid design approach, that combines CMOS and protected logic styles, paving the way to the new research area of the ``protected vs non-protected'' co-design.

We then used our flow to protect an embedded processor realized in CMOS and augmented with instruction set extension. Contrary to past works, which typically have realized new instructions with the solely goal of performances, we have designed our instructions having security as the primary objective, and we have explored different partitions of a block cipher between protected and unprotected logic. Finally, we explored whether the presence of fault detection circuits affects the resistance against attacks based on power analysis.