I am a Professor in the Informatics Faculty at USI Lugano, Switzerland.
I am interested in the interaction between compiler and architecture design, particularly in the field of embedded systems.
My research interests include: The automation of embedded processor customization; The definition of innovative reconfigurable fabrics — both in terms of how to architect them and how to compile onto them; Approximate Computing and Approximate Logic Synthesis: the process of approximating any gate-level circuit automatically, under a given error constraint; High Level Synthesis and Design Space Exploration: how to raise the level of abstraction of HLS by automatically selecting the right design decisions (such as 'pragmas') for the programme; Fuzzing: generating test cases automatically to complement manually written test suites, in the quest to find bugs in software.
My current group: Rodrigo Otoni (Postdoc), Morteza Rezaalipour (PhD student), Riccardo Felici (PhD student), Cristian Tirelli (PhD student), Marco Biasion (Master Student) Francesco Costa (Master Student). Alumni: Ilaria Scarabottolo (PhD student and then Postdoc), Lorenzo Ferretti (PhD student and then Postdoc), Georgios Zacharopoulous (PhD student), Giovanni Ansaloni (PhD student and then Postdoc), Paolo Bonzini (PhD student).Nice things:
I won the Credit Swiss Best Teaching Award! Picture here
I organize an event to celebrate the United Nation International Women and Girls in Science Day at USI Informatics every year
Our students in the USI Programming Team scored close to TOP 5% in the SWERC Programming Contest in 2017/2018 and in 2018/2019. We also participated and got excellent results in 2022/2023 and in 2023/2024.
Selected Recent Publications:
TCAD-2026: Morteza Rezaalipour, Marco Biasion, Francesco Costa, Cristian Tirelli, Lorenzo Ferretti, Rodrigo Otoni, George A Constantinides, Laura Pozzi. Approximate Logic Synthesis via Iterative SMT-based Subcircuit Rewriting, TCAD 2026: 1-14. DOI 10.1109/TCAD.2025.3638267 find the paper pdf here
DATE2025:Cristian Tirelli, Rodrigo Otoni, Laura Pozzi. Monomorphism-Based CGRA Mapping Via Space and Time Decoupling, DATE 2025: 1-6.
ARC2025: Yuxuan Wang, Cristian Tirelli, Lara Orlandic, Juan Sapriza, Rubén Rodríguez Álvarez, Giovanni Ansaloni, Laura Pozzi, David Atienza: An MLIR-Based Compilation Framework for CGRA Application Deployment, ARC 2025
ACM2024: Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, José Angel Miranda, David Atienza, Laura Pozzi: SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs, ACM J. Emerg. Technol. Comput. Syst. 20(3): 8:1-8:26 (2024)
EMSE2024:Riccardo Felici, Laura Pozzi, Carlo A. Furia: HyperPUT: generating synthetic faulty programs to challenge bug-finding tools Empir. Softw. Eng. 29(2): 38 (2024)
DSN-W2023:Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi. A Parametrizable Template for Approximate Logic Synthesis, DSN-W 2023: 175-178 find the paper pdf here
DATE2023:Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi. SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures, DATE 2023: 1-6.
TODAES2023:Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi. Graph Neural Networks for High-Level Synthesis Design Space Exploration, ACM Trans. Design Autom. Electr. Syst. 28(2): 25:1-25:20 (2023).
TCAD2022:Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi. A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 840-853 (2022).
PIEEE2020: Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda. Approximate Logic Synthesis: A Survey, Proc. IEEE 108(12): 2195-2213 (2020), special issue on Approximate Computing. 2020.