About me

I am a Ph.D. student in informatics at Università della Svizzera italiana (USI) from July 2016. I am currently working under the supervision of Prof. Laura Pozzi in a research group with Dr. Giovanni Ansaloni, Georgios Zacharopoulos and Ilaria Scarabottolo. I've started working with the research group in January 2016 during my master thesis and in June 2016 I obtained a master degree of Science in Informatics at the Università della Svizzera italiana. Before the master at USI, I obtained a bachelor degree of Science in Informatics in April 2014 at University of Milano-Bicocca. After the bachelor, before starting the master in Switzerland, I have worked for 6 months as research assistant for the IRALab research group at University of Milano-Bicocca.

Research

High Level Synthesis (HLS) frameworks are used to describe hardware designs in high-level languages (C/C++), without burdening developers with the error-prone task of specifying their implementation in detail. The HLS process is usually controlled by user-given directives (e.g., directives to set whether or not to unroll a loop) which influence the resulting implementation area and latency. Nonetheless, the correlation among directives and resulting performance is often dif ficult to foresee and to quantify, and the high number of available directives leads to an exponential explosion in the number of possible con gurations. In addition, sampling the design space involves a time-consuming hardware synthesis, making a brute-force exploration infeasible beyond very simple cases.

For a given design, only few directive settings result in Pareto-optimal solutions (with respect to metrics such as area, run-time and power), while most are dominated. The design space exploration problem aims at identifying Pareto optimal implementations while synthesising only a small portion of the possible con gurations from the design space.

Addressing this challenge, my ongoing research effort focuses on the development of methodologies able to smartly navigate the design space to retrieve a close approximation of the real Pareto solutions, synthesising only a small fraction of the possible designs.

Teaching

As Ph.D. student for USI, I have been teaching assistant for the following courses:

Semester Academic Career Year
Fall Bachelor 2018
Computer Architecture (currently doing TA)
Spring Master 2018
Advanced Computer Architecture
Fall Bachelor 2017
Automata & Formal languages
Spring Bachelor 2017
System Programming
Fall Bachelor 2016
Automata & Formal languages

Projects

Cluster-Based Design Space Exploration

A cluster-based heuristic that, by only exploring a subset of possible configurations for an High Level Synthesis design, is able to retrieve a close approximation of its Pareto Frontier of non-dominated implementations.
The framework identifies regions of interest in the design space, and iteratively searches for new solutions within such regions, or in their combinations.
More information at this link.

Lattice-Traversing Design Space Exploration

A Lattice-Traversing local search strategy that, by exploring Pareto-solution neighbours, is able to retrieve a close approximation of the Pareto Frontier of a design space.
The framework exploit the property of Pareto-solutions to share high similarity among dominant configurations and iteratively searches for new configuration to imporve the explored Pareto-front.
More information at this link.

Publications

Journals

2016 An Indoor Localization System for Telehomecare Applications
A. L. Ballardini, L. Ferretti, S. Fontana, A. Furlan & D. G. Sorrenti, D. G. An Indoor Localization System for Telehomecare Applications. IEEE Transactions on Systems, Man, and Cybernetics: Systems, 2016
2018 Cluster-Based Heuristic for High Level Synthesis Design Space Exploration
L. Ferretti, G. Ansaloni, and L. Pozzi. Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. IEEE Transactions on Emerging Topics in Computing, 2018.
2018 RegionSeeker: Automatically Identifying and Selecting Accelerators from Application Source Code
G. Zacharopoulos, L. Ferretti, E. Giaquinta, G. Ansaloni, L. Pozzi. RegionSeeker: Automatically Identifying and Selecting Accelerators from Application Source Code. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
2018 Lattice-Traversing Design Space Exploration for High Level Synthesis
L. Ferretti, G. Ansaloni, and L. Pozzi. Lattice-Traversing Design Space Exploration for High Level Synthesis. IEEE International Conference on Computer Design, 2018.

Master thesis

2017 Exploring the potential of High Level Synthesis tools for FPGAs
Lorenzo Ferretti. Exploring the potential of High Level Synthesis tools for FPGAs. (Thesis awarded with Premio Swissengineering Ticino 2017)