Sepideh Asadi
Sepideh Asadi

Sepideh Asadi
PhD Candidate

Università della Svizzera italiana (USI)
Informatics, Level 2
Via Giuseppe Buffi, 13
CH-6904, Lugano, Switzerland
+41 58 666 4312
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CV (pdf), DBLP, Google Scholar, LinkedIn

About me

I am a final year PhD student in computer science at USI Lugano Formal Verification and Security Lab advised by Prof. Natasha Sharygina. I am broadly interested in software verification with a specific focus on automated symbolic model-checking, incremental verification of C programs, and SAT/SMT solving. I have contributed to developing of UpProver, a bounded model checker for incrementally verifying software revisions. I have also contributed in design of HiFrog, an SMT-based BMC with theory refinement algorithm.


PhD Candidate in Computer Science

Università della Svizzera italiana (USI Lugano), Lugano, Switzerland, Mar 2016 - present

M.Sc in Information Technology/ Secure Communications

Iran University of Science & Technology (IUST), Tehran, Iran,

B.Sc Electrical Engineering/ Electronics

Zanjan University, Zanjan, Iran,

Further Education

Aug 2017
SAT/SMT & Symbolic Computation Summer School · MPI Informatics, Saarbrücken, Germany
Aug 2016
Dependable Software Systems Engineering · Marktoberdorf Summer School, Germany
Oct 2016
Workshop on Software Correctness and Reliability · ETH Zürich
Jun 2016
SAT/SMT & Automated Reasoning Summer School · Lisbon, Portugal
Spring 2016
Computer Aided Verification · Università della Svizzera italiana, Lugano, CH


Academic Experience

Teaching Assistant

Bachelor Projects · Università della Svizzera italiana, Lugano, CH
Fall'18, Fall'19
Software Design and Modelling · Università della Svizzera italiana, Lugano, CH
SP'17, SP'18, SP'20
Theory of Computation · Università della Svizzera italiana, Lugano, CH
Fall'16, Fall'17
Fundamentals of Informatics · Università della Svizzera italiana, Lugano, CH

Conference Talks & Invited Talks

Nov 2020
Farkas-Based Tree Interpolation, SAS 2020· Chicago, USA Online
[ slide | video]
Sep 2020
UpProver: Incremental Verification by SMT-based Summary Repair, FMCAD 2020· Online
[ slide | short-video | full-video ]
Nov 2018
Function Summarization Modulo Theories, LPAR 2018 · Awassa, Ethiopia
[ slide ]
Sep 2017
11th Alpine Verification Meeting (AVM) · Visegrád, Hungary
[ slide ]
Apr 2017
HiFrog: Interpolation-based Software Verification using Theory Refinement, TACAS 2017 · Uppsala, Sweden
Jan 2013
A survey on formal methods · Security Study Group (SSG) of IT organization of Iran
Jan 2012
Formal verification of security protocols · Iran Telecommunication Research Center (ITRC), Tehran, Iran


Sub-reviewing ACM Journal of Computing Surveys (CSUR),
Sub-reviewing papers on international Conferences: CAV ('20, '19, '18); TACAS ('20, '18, '17); VMCAI ('20); SAT ('20,'19); FM ('19, '18, '16); AAAI ('19); FMCAD (20', '19, '18, '17); HVC ('17).
Sub-reviewing papers on international workshops: SMT('20), MARS('20)

Work Experience