Laura Pozzi: Publication List
International Journals or Book Chapters
Alex Orailoglu, Laura
Pozzi. Guest Editorial, Special
Section on the IEEE Symposium on Application Specific Processors 2008,
IEEE Transactions on Computer-Aided Design
of
Integrated Circuits and Systems, 2009, to appear.
Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann
Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep
Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne.
Evaluating Resistance of MCML
Technology to Power Analysis Attacks Using a Simulation-Based
Methodology. Transactions on Computational Science IV, Special
Issue on Security in Computing. Lecture Notes in Computer Science,
Springer, 4:
230---243, 2009
Paolo Bonzini and Laura Pozzi Recurrence-Aware
Instruction Set Selection for Extensible Embedded Processors IEEE
Transactions on Very Large Scale Integration (VLSI) Systems,
16(10):1259--67, October 2008.
Partha Biswas, Nikil Dutt,
Paolo Ienne, and Laura Pozzi. Introduction
of Architecturally
Visible Storage in
Instruction Set Extensions
IEEE
Transactions on Computer-Aided Design
of
Integrated Circuits and Systems, 26(3): 3423-55, March 2007.
Laura Pozzi and Paolo Ienne. Automatic Instruction Set Extension.
In Paolo
Ienne and Rainer Leupers, editors,
Customizable Embedded Processors, Systems on Silicon Series, chapter
7. Morgan Kaufmann, San Mateo, Calif., 2006.
Miljan
Vuletic, Laura Pozzi, and Paolo Ienne. Virtual
memory window
for application-specific reconfigurable coprocessors. IEEE
Transactions on Very Large Scale Integration (VLSI) Systems,
14(8):910-15, August 2006.
Andre DeHon, Yury Markowsky, Eylon Caspi, Michael Chu, Randy Huang,
Stylanos Perissakis, Laura Pozzi, Joseph Yeh and John Wawrzynek. Stream Computation Organized for
Reconfigurable Computing. Journal
of Microprocessors and
Microsystems, 30(6):334--354, September 2006.
Partha Biswas,
Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and
Paolo Ienne. ISEGEN:
An iterative improvement-based ISE generation
technique for fast customization of processors. IEEE
Transactions
on Very Large Scale Integration (VLSI) Systems,
14(7):754-62, July
2006.
Laura Pozzi, Kubilay
Atasu, and Paolo Ienne. Exact
and
approximate algorithms for the extension of embedded processor
instruction sets. IEEE Transactions on Computer-Aided Design
of
Integrated Circuits and Systems, 25(7):1209-29, July 2006.
Miljan Vuletic,
Laura Pozzi, and Paolo Ienne. Seamless Integration of Hardware
and Software in Reconfigurable Computing Systems.
IEEE Design and
Test
of Computers, IEEE Design and Test of Computers, 22(2):102–13,
March–April 2005.
Kubilay Atasu, Laura Pozzi, and Paolo Ienne. Automatic Application-Specific
Instruction-Set Extensions under Microarchitectural Constraints,
International Journal of
Parallel Programming, 31(6), Dec 2003.
International
Conferences-Symposia-Workshops
-------2009-------
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi. Heterogeneous coarse-grained processing
elements: A template architecture for embedded processing acceleration.
In Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition, Nice, April 2009.
-------2008-------
Paolo Bonzini, Giovanni
Ansaloni and Laura
Pozzi. Compiling
Custom Instructions onto
Expression-Grained Reconfigurable Architectures. In Proceedings of the
International Conference on
Compilers, Architectures, and Synthesis for Embedded Systems,
Atlanta, GA, October 2008.
Giovanni
Ansaloni, Paolo Bonzini and Laura
Pozzi. Design
and Architectural Exploration of Expression-Grained Reconfigurable
Arrays. In
Proceedings of the IEEE Symposium on Application Specific Processors,
Anaheim, Calif, June 2008.
-------2007-------
Francesco Regazzoni, Stephane Badel, Thomas Eisenbarth,
Johann Grosschadl, Axel Poschmann, Zeynep Toprak Deniz, Marco
Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne. Simulation-based Methodology for
Evaluating DPA-Resistance of Cryptographic Functional Units;
Application to CMOS and MCML Technologies. In Proceedings of the SAMOS
Conference,
Samos, Greece, July 2007.
Paolo Bonzini, Dilek Tekbas and
Laura
Pozzi. A Study of Energy
Savings in Customisable Processors.
In Proceedings of the SAMOS
Workshop, Samos, Greece, July 2007.
Paolo Bonzini and Laura
Pozzi. A Retargetable
Framework for Automated Discovery of Custom Instructions. In Proceedings of the
International Conference on Application-Specific Systems, Architectures
and Processors, Montreal, July 2007.
Laura
Pozzi and Pierre Paulin. A Future of Customisable Processors:
are we there yet? In Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition, Nice, April 2007.
Paolo Bonzini and Laura
Pozzi. Polynomial-Time
Subgraph Enumeration for Automated Instruction Set Extension. In Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition, Nice, April 2007.
-------2006-------
Paolo Bonzini and Laura
Pozzi. Code Transformation
Strategies for Extensible Embedded Processor. In Proceedings
of IEEE CASES
International Conference on Compilers Architectures and Synthesis for
Embedded Systems. Seoul Oct 2006.
Partha Biswas, Nikil Dutt,
Paolo Ienne, and Laura Pozzi. Automatic
identification of application-specific functional units with
architecturally visible storage. In Proceedings of the Design,
Automation and Test in Europe Conference and Exhibition, pages
212-17, Munich, March 2006. Best Paper Award
Nominee.
Johann Grosschadl,
Stefan Tillich, Paolo Ienne, Laura
Pozzi, and Ajay K. Verma. Combining
algorithm exploration with instruction set design: A study in elliptic
curve cryptography. In Proceedings of the Design,
Automation
and Test in Europe Conference and Exhibition, pages 218-23,
Munich, March 2006.
Partha Biswas, Sudarshan
Banerjee, Nikil Dutt, Paolo Ienne, and
Laura Pozzi. Performance
and energy benefits of instruction set extensions in an FPGA soft
core. In Proceedings of the 19th International Conference on
VLSI Design, pages 651-56, Hyderabad, India, January
2006. Best Paper Award Nominee.
-------2005-------
Laura Pozzi and Paolo
Ienne. Exploiting
pipelining to relax register-file port constraints of instruction-set
extensions. In Proceedings of the International Conference on
Compilers, Architectures, and Synthesis for Embedded Systems,
pages 2-10, San Francisco, Calif., September 2005.
Christophe Dubach, Miljan
Vuletic,
Laura Pozzi, and Paolo Ienne. Enabling
unrestricted automated synthesis of portable hardware accelerators for
virtual machines. In Proceedings of the International
Conference on Hardware/Software
Codesign and System Synthesis, Jersey City, N.J., September 2005.
Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and Paolo
Ienne. ISEGEN:
generation of high-quality instruction set extensions by iterative
improvement. In Proceedings of the Design, Automation and Test
in Europe Conference and Exhibition, Munich, March 2005.
-------2004-------
Partha
Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and Paolo Ienne. Fast
automated generation of high-quality instruction set extensions for
processor customization. In Proceedings of the 3rd Workshop on
Application
Specific Processors, Stockholm, September 2004.
Miljan Vuletic, Laura Pozzi,
and Paolo Ienne. Programming
transparency and portable hardware interfacing: Towards general-purpose
reconfigurable computing. In Proceedings of the 15th
International Conference on Application-specific Systems, Architectures
and Processors, Galveston, Tex., September 2004.
Diviya Jain, Anshul Kumar, Laura Pozzi, and Paolo Ienne. Automatically customising VLIWarchitectures with coarse grained application-specific
functional units. In Proceedings of the 8th International
Workshop on Software and Compilers for Embedded Systems, Amsterdam,
September 2004.
Miljan Vuletic, Laura Pozzi, and Paolo Ienne. Dynamic
prefetching in the virtual memory window of portable reconfigurable coprocessors. In
Proceedings of the 14th International Conference on Field-Programmable
Logic and Applications, Antwerp, Belgium, August 2004.
Partha Biswas, Kubilay Atasu, Vinay Choudhary, Laura Pozzi, Nikil Dutt,
and Paolo Ienne. Introduction
of local memory elements in instruction set extensions. In
Proceedings of the 41st Design Automation Conference, San Diego,
Calif., June 2004.
Miljan Vuletic, Laura Pozzi, and Paolo Ienne. Virtual
memory window for application-specific reconfigurable coprocessors.
In Proceedings of the 41st Design Automation Conference,
San Diego, Calif., June 2004.
Miljan Vuletic, Laura Pozzi, and Paolo Ienne. Virtual
memory window for a portable reconfigurable cryptography coprocessor. In Proceedings of the
12th IEEE Symposium on Field-Programmable Custom Computing Machines,
Napa
Valley, Calif., April 2004.
Miljan Vuletic, Ludovic Righetti, Laura Pozzi, and Paolo Ienne. Operating system support for interface virtualisation of reconfigurable coprocessors.
In Proceedings of the Design, Automation and Test in Europe Conference
and Exhibition, Paris, February 2004.
-------2003-------
Miljan Vuletic, Ludovic Righetti, Laura Pozzi, and Paolo Ienne. Operating System Support for Interface Virtualisation
of Reconfigurable Coprocessors, In Proceedings of WASP-2,
2nd Workshop onApplication Specific Processors, San Diego, CA, December
2003.
Armita Peymandoust, Laura Pozzi, Paolo Ienne, and Giovanni De Micheli. Automatic
Instruction Set Extension and Utilization for Embedded Processors,
In Proceedings of the 14th International Conference on ASAP,
Application-specific Systems, Architectures and Processors, The Hague,
The Netherlands, June 2003.
Kubilay Atasu, Laura Pozzi, and Paolo Ienne.
Automatic Application-Specific Instruction-Set Extensions under
Microarchitectural Constraints, In Proceedings of 40th DAC
Design Automation
Conference, Los Angeles, June 2003. Best
Paper Award.
-------2002-------
Ajay Kumar Verma, Kubilay Atasu, Miljan Vuletic,
Laura Pozzi, and Paolo Ienne.
Automatic Application-Specific Instruction-Set Extensions under
Microarchitectural Constraints, In Proceedings of WASP-1 the
1st Workshop onApplication Specific Processors, Istanbul, November
2002.
Laura Pozzi, Miljan Vuletic, and Paolo Ienne.
Automatic topology-based Identification of instruction-set Extensions
for Embedded Processors, Poster paper in Proceedings of
the Design, Automation and Test in Europe Conference and Exhibition,
page 1138, Paris, March 2002. Extended
Version Here
-------older-------
A.Alippi, W.Fornaciari, L.Pozzi, M.G.Sami, Determining
the Optimum Extended Instruction-Set Architecture for
Application-Specific Reconfigurable VLIW CPUs, RSP'01 - 12th
IEEE International Workshop on Rapid System Prototyping, Monterey, CA,
June 25-27, 2001
A.Alippi, W.Fornaciari, L.Pozzi, M.G.Sami, Determining
the Optimum Extended Instruction-Set Architecture for
Application-Specific Reconfigurable VLIW CPUs, (poster version
of the above) Proc. ACM International Symposium on Field Programmable
Gate Arrays, Monterey, California, 9-11 February, 2000.
A.Alippi, W.Fornaciari, L.Pozzi, M.G.Sami, A
DAG-Based Design Approach for Reconfigurable VLIW Processors",
IEEE International Conference on Design and Test in Europe, Munich,
Germany, 9-12 March, 1999, pag. 778-780. Extended
Version Here.
W.Fornaciari, L.Pozzi, M.G.Sami, Reconfigurable
Processing as a Target Architecture for Co-Design, Poster paper,
presentation only , 6th ACM IEEE International Workshop on
Hardware/Software Co-Design, Seattle, Washington, 15-18 March, 1998.
F.Fummi, A.Marshall, L.Pozzi, M.G.Sami, Minimising
the Application Time for Manufacturer Testing of FPGAs,
poster paper, Proc. ACM International Symposium on Field Programmable
Gate Arrays, Monterey, California, 22-24 February, 1998, pag 259.
F.Ferrandi, F.Fummi, L.Pozzi, M.G.Sami, Configuration-Specific
Test Pattern Extraction for Field Programmable Gate Arrays, Proc.
IEEE International Symposium on Defect and Fault Tolerance in VLSI
Systems,
Paris, France, 20-22 October, 1997, pag.
National Journals
W.Fornaciari, L.Pozzi, M.G.Sami,I Processori Riconfigurabili:
un'Alternativa Flessibile ai Processori Dedicati, Alta Frequenza,
Rivista di Elettronica, January 1999.
Technical Reports
Paolo Ienne, Laura Pozzi, Miljan Vuletic. On the
Limits of Processor Specialisation by Mapping Dataflow Sections on
Ad-hoc Functional Units.CS
Technical Report 01/376. December 2001. UPDATED
VERSION HERE
Laura Pozzi, Miljan Vuletic, and Paolo Ienne. Automatic
Topology-Based Identification of Instruction-Set Extensions for
Embedded Processors. CS Technical Report 01/377. December 2001.
W.Fornaciari, G.Meardi, L.Pozzi, M.Sami, The
PoliMorph Project: an Automated Design Tool to Effectively Exploit
Run-Time Reconfiguration, TR-99.49, Politecnico di Milano, 1999.
L.Pozzi, Compilation Techniques for
Exploiting Instruction Level Parallelism, a Survey TR-99.2,
Politecnico di
Milano, February 1999
A.Alippi, W.Fornaciari, L.Pozzi, M.G.Sami, A DAG-Based Design Approach for
Reconfigurable VLIW Processors TR-98.104, Politecnico di
Milano, December
1998, extended version of DATE99 paper
L.Pozzi, Test generation for FPGA logic: an
implicit methodology TR-98.94, Politecnico di Milano, October
1998
PhD Thesis
Laura Pozzi Methodologies
for
the Design of Application-Specific Reconfigurable VLIW Processors,
PhD
Thesis, Politecnico di Milano, DEI, Jan 2000.
Other
L.Pozzi, "Design and Implementation of a Radix-4 Divider by Digit
Recurrence in a Sea of Gates", Final Project for the Engineering
Degree, Politecnico di Milano, Milano, Italy, April 1996.