Seminars at the Faculty of Informatics

Field Progeammable Compressor Tree(FPCT): A reconfiguarable hard IP block to improve FPGA performance for arithmetic circuits. Seminar by Alessandro Cervero, June 17th, 17.00

The Faculty of Informatics is pleased to announce a seminar given by Alessandro Cervero

TITLE: Field Progeammable Compressor Tree(FPCT): A reconfiguarable  hard IP block to improve FPGA performance for arithmetic circuits
SPEAKER: Alessandro Cevrero (EPFL)
DATE: Wednesday 17th June, 2009
PLACE: USI Università della Svizzera italiana, room SI-008, Informatics building (Via G. Buffi 13)
TIME: 17.00

A Field Programmable Compressor Tree (FPCT) is a programmable IP core integrated into an FPGA or other reconfigurable device to improve arithmetically intensive applications. Compressor trees, e.g., Wallace or Dadda Trees, are a class of arithmetic circuits that generalizes multi-input integer addition, including partial product reduction for parallel multiplication, and other accumulation-oriented arithmetic kernels, such as FIR filters. The FPCT is a flexible alternative to DSP blocks-which contain fixed-bitwidth multipliers and pipelined high-throughput multiply-accumulate (MAC) units-that are embedded in modern high-performance FPGAs, due to the increasing demand for high throughput signal processing applications. The FPCT takes advantage of recently published dataflow transformations that identify and expose compressor trees; DSP blocks, in contrast, do not expose the compressor trees within their multipliers to the user, and cannot benefit from these transformations. Compared to state-of-the-art compressor tree synthesis methods targeting the Altera Stratix II (90nm) FPGA, a relatively small FPCT, realized in 90nm Artisan standard cell technology increased the maximum operating frequency by 1.61x on average in parallel accumulation mode and by 2.59x on average when pipelined for high throughput, with an average increase in area utilization of 5.31x.
The operating frequencies of the FPCT in parallel and pipelined mode were competitive with the DSP blocks in the 90nm Xilinx Virtex-4 and Altera's Stratix II.

Alessandro Cevrero Received the B.S degree in electrical Enginnering from Politecnico di Torino in 2005. He received an M.S.
Degree in Micro- and Nano-technologies for Integrated Systems, issued jointly from the INP Grenoble, Politecnico di Torino, and EPFL in 2007.
In October 2007, he joined both the Microelectronics Systems Laboratory and the Processor Architecture Laboratory at EPFL as research assistant and worked in the field of full custom/semicustom digital VLSI design.
He started his PhD at EPFL in March, 2008. His research interests include design of VLIS system,  arhitecture and physical implementation of high speed arithmetic  blocks, reconfigurable datapaths, cryptographic enginering  and computer architecture.

HOST: Francesco Regazzoni (ALaRI)

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