ENLARGING THE SCOPE OF AUTOMATION
IN CUSTOM INSTRUCTION IDENTIFICATION AND SYNTESIS
Custom Instructions (CIs) are special, complex instructions that are added to a processor in order to make it better targeted to a particular application to be served, resulting in higher performance and better power efficiency.
The automatic identification and synthesis of such instructions is the process of devising them automatically from the application source code. The state of the art of automatic CI identification has advanced considerably in the past 15 years; however, several challenges still lay ahead, and the challenges here identified were inspired by reading a recent paper [*], that set out to understand the sources of inefficiencies of general-purpose processors, both in terms of performance and power. An important consideration is made at the end of the paper study: the only way to bridge the gap between sw execution, and dedicated hardware execution, is to specialize the baseline processor. The paper indeed adds more and more complex instruction to a baseline processor under consideration, identifying these instructions manually and terming them magic because of their complexity, and achieving some outstanding performance and power improvements.
This project aims at identifying those same instructions, but in an automatic way; i.e., devising algorithms that can identify and synthesize those instructions without programmer intervention. The characteristics that make these instructions special, and beyond the current challenges of state of the art tools, are: they cluster 100s of original operations into a single instruction and they are tightly connected to custom data storage elements.
The project extends therefore the state of the art in Custom Instruction Identification and Synthesis methodologies, combining them with compiler transformations such as loop unrolling and local memory detection, and finally analyzing the tradeoff of mapping such extensions onto reconfigurable logic.
The project covers two PhD positions (one on Identification and one on
Synthesis of Custom Instructions) and one postdoc position.
[*] Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex
Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis,
and Mark Horowitz. Understanding sources of inefficiency in
general-purpose chips. Commun. ACM, 54(10): 85 - 93, 2011.